Level-shifter circuits are known in the art. Integrated circuits use level-shifter circuits to bridge different voltage domains, in particular to change the voltage of a signal from a first voltage to a second voltage. For instance, low-voltage (LV) digital and mixed signal circuits are often combined with high-voltage (HV) driving capabilities for MEMS (micro-electromechanical systems) applications. The driving circuits often use a HV NMOS (high-voltage n-type metal-oxide semiconductor) and a HV PMOS (high-voltage p-type metal-oxide semiconductor) as the pull-up and pull-down device, respectively. While the HV NMOS can be controlled using standard LV logic, an appropriate HV control signal must be applied to the gate of the HV PMOS for proper operation. Level-shifter circuits are used to generate the appropriate HV signals to control the HV PMOS.
Insulated gate field effect transistors are conventionally referred to as MOSFETs or MOS, regardless of whether the gate is constructed of metal or the gate insulator is constructed of silicon-dioxide. Low-voltage MOSFETs have conventional sources and drains. IC process options may be available (including gate insulator thickness and material) to give differences in operating voltage, although such variations will be collectively referred to herein as LV MOS or simply NMOS and PMOS. Double-diffused MOS (DMOS) is a common construction for high-voltage transistors. Variant constructions include laterally-diffused MOS (LDMOS) and extended-drain PMOS (EDPMOS).
As will be discussed in greater detail later herein, prior art level shifter circuits are susceptible to gate-oxide breakdown resulting from transistor sub-threshold leakage unless input signals are toggled or refreshed at sufficient intervals. In view of this problem, there is a need for a high-voltage level shifter circuit with low static power consumption that does not require refreshing or additional pull-up elements. The present invention is directed to this need.